Low cost and highly reliable radiation hardened latch design in 65 nm
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Low cost and highly reliable radiation hardened latch design in 65 nm CMOS technology
As a consequence of technology scaling down, gate capacitances and stored charge in sensitive nodes are decreasing rapidly, which makes CMOS circuits more vulnerable to radiation induced soft errors. In this paper, a low cost and highly reliable radiation hardened latch is proposed using 65 nm CMOS commercial technology. The proposed latch can fully tolerate the single event upset (SEU) when pa...
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